1. Field of the Invention
This invention relates to a method of producing a GaAs single crystal substrate, more particularly to a heat treatment method used after growth of the single crystal. The technology provided by the invention can be effectively used in a method of producing a GaAs substrate that provides a substrate which is highly suitable for an electronic device such as an FET.
2. Description of the Related Art
GaAs, a compound semiconductor, is industrially produced mainly by methods such as the liquid encapsulated Czochralski method (LEC method) and the horizontal Bridgman method. Since these single crystal growth methods grow the single crystal in a crystal growth furnace having a temperature gradient, the temperature environment of the growing crystal is different at different parts thereof. This results in a grown crystal with uneven internal characteristics. When such a crystal is sliced into wafers as it is and the wafers are used as the substrate for electronic devices, the internal unevenness of the crystal shows up in the form of dispersion among the characteristics of the individual devices and leads directly to reduced device yield. In the fabrication of such high-speed devices as discrete FETs (field-effect transistors) and integrated circuits on a GaAs wafer, for example, characteristic irregularities in the wafer surface lead to differences among the threshold voltages of the individual FETs or the FETs on one and the same chip, making it impossible to obtain products with identical characteristics. For eliminating internal crystal unevenness, Rumsby et al. proposed a method for annealing the single crystal ingot at a high temperature following its growth (D. Rumsby, R. M. Ware, B. Smith, M. Tyjerg, and M. R. Brozel; IC Symposium, Phoenix, Technical Digest (1983) 34). This proposal was followed by the development of various other ingot annealing methods as taught, for example, by Japanese Patent Public Disclosures Sho 61-201700, Sho 61-222999, Sho 62-21699, Sho 62-162700 and Sho 2-21800.
The method of Rumsby is, however, not able to reduce the dispersion in FET threshold voltage to an adequate degree.
While the various methods proposed in the patent applications filed after the announcement of the Rumsby method have auxiliary effects such as increasing the efficiency of the annealing operation or are able to increase the resistivity of low resistivity crystals, they are not capable of reducing the dispersion in threshold voltage within the wafer to a satisfactory degree.
Earlier research by the inventors shows that two highly effective methods for evaluating the uniformity of GaAs wafers are (1) to observe the cathode luminescence of the wafer surface and (2) to measure the density of the small flaws (egg-shaped pits) that appear when the wafer is etched with AB etchant (2ml H.sub.2 O, 8mg AgNO.sub.3, 1 g CrO.sub.3, 1 ml HF). For capturing the cathode luminescence image, it is preferable to use a scanning electron microscope modified by the installation of a reflecting mirror and a light detector since this facilitates the measurement and also, by enabling the luminescence image to be obtained with a resolution of 0.5-1 .mu.m, makes it possible to better examine the microscopic uniformity of the wafer surface.
The inventors examined the luminescence images of the surfaces of GaAs single crystals which had been subjected to conventional heat treatment. Irregular light emission distribution was observed irrespective of the method used. This irregularity of the cathode luminescence image suggests uneven distribution within the crystal of characteristic defects such as impurities and EL2, and indicates that the required degree of uniformity has not yet been achieved.
The inventors next used method (2) to examine crystals grown by the LEC method. After fabricating FETs and evaluating their characteristics, they removed the FET electrodes by etching with AB etchant. For each of the FETs, they then investigated the correlation between the FET characteristics and the egg-shaped pits that appeared. As a result, they discovered that the FET characteristics are severely degraded when egg-shaped pits appear at the gate region of the device. (See, for example, Yamamoto et al.: "Microscopic defects in semi-insulating GaAs and their effects on the FET device characteristics" (International Conference on the Science and Technology of defect control in semiconductors, Yokohama (1989.8)) and Yamamoto et al.: "Microscopic defects in semi-insulating GaAs and their effects (Journal of Electrochemical Science, Volume 136 (1989) P.3098)). Using the same method, they next measured the egg-shaped pit density of GaAs wafers which had been subjected to the aforementioned conventional heat treatment. The density was observed to be high (&gt;10.sup.4 cm.sup.-2) in all cases and it was found that FETs fabricated on the wafers exhibited a wide range of threshold voltages.
Another effective way for evaluating uniformity is to measure the microscopic resistivity distribution in the wafer surface and still another is to observe the wafer surface profile after etching with AB etchant. In particular, it is known that there is a one-to-one correlation between FET threshold voltage dispersion and microscopic resistivity distribution and that the dispersion in threshold voltage decreases in proportion as the dispersion in resistivity decreases (Asai et al., Shingaku Giho, CPM87-55.1 (1987). Moreover, since etching with AB etchant proceeds through an electrochemical reaction between the etching liquid and the wafer, the etching rate depends on the Fermi level of the GaAs substrate and, therefore, if differences arise in the Fermi level between different points on the wafer surface, irregularities will be produced owing to differences in etching rate.
Taking the foregoing into consideration, the inventors concluded that there are five conditions which determine whether a GaAs single crystal substrate exhibits uniform characteristics making it optimum for use as the substrate of electronic devices:
(a) Uniform cathode luminescence. PA0 (b) Low density of the minute defects (egg-shaped pits) which appear when the wafer is AB-etched. PA0 (c) Small dispersion in the microscopic resistivity distribution. PA0 (d) Flat wafer surface profile after AB etching. PA0 (e) Dislocation density not larger than that of the as-grown crystal.
The inventors further concluded that all of these conditions can be met by developing an appropriate annealing method.
Actually, a number of annealing methods more complex than the conventional ingot annealing method have recently been proposed. However, none of them is able to produce a crystal which satisfies all of the requirements (a) to (e). In one such method set out in Japanese Patent Application Sho 63-042508 the density of the egg-shaped pits that appear with AB etching is reduced by cooling the ingot after it has been annealed at a temperature exceeding 1100.degree. C. While this method does indeed reduce the minute defect density and, moreover, results in an EDP (etch pit density, an index of the dislocation density) of the same level as that of the as-grown crystal, it does not achieve a uniform cathode luminescence image. Another method proposed in Japanese Patent Public Disclosure Sho 62-226900 realizes uniform microscopic resistivity distribution by gradual annealing the ingot at high, low and medium temperatures. However, this method has drawbacks in that the cathode luminescence image is irregular, the egg-shaped pit density is greater than 10.sup.5 cm.sup.-2, a value as high as that of the as-grown crystal, and the EDP is higher than that of the as-grown crystal. In addition, Look et al. have proposed an annealing method in which GaAs crystal is first annealed at a high temperature to once convert it to P type for reduction of EL2 defects and is then annealed at a medium temperature (D. C. Look, P. W. Yu, M. W. Theis, W. Ford, G. Mathur, J. R. Sizelore, D. H. Lee, and S. S. Li; Appl. Phys. Lett. 49, 1083 (1986)). However, this method fails to satisfy any of the conditions (a) to (e).
As can be seen from the foregoing, the earlier methods are able to satisfy only 1 or 2 of the conditions (a) to (e) at most and none is able to satisfy all five conditions.
The inventors therefore developed a two-stage wafer annealing method capable of producing a crystal satisfying all of (a)-(e) (Japanese Patent Application Hei 1-199202). While this was the first annealing method meeting all of conditions (a)-(e), further tests revealed that it left room for improvement in respect of condition (c) relating to microscopic resistivity distribution and condition (d) relating to flatness of the wafer surface profile after AB etching.